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18 - bit, 2 msps precision sar differential adc data sheet ad4003 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2016 analog devices, inc. all r ights reserved. technical support www.analog.com features throughput: 2 msps maximum inl: 1. 0 lsb ( 3.8 ppm) maximum guaranteed 18 - bit no missing codes low power 9 .5 mw at 2 msps (vdd o nly) 80 w at 1 0 k sps , 1 6 mw at 2 msps ( t otal) snr : 100.5 db typical at 1 k hz, 99 db typical at 100 k hz thd: ? 123 db typical at 1 k hz, ? 100 db typical at 1 00 k hz ease of use features reduce system power and complexity input o ver v oltage c lamp circuit reduced n on linear i nput charge kick back high - z m ode long acquisition phase input s pan c ompression fast conversion time allows l ow sp i clock rates spi - programmable modes, r ead/ w rite capability , s tatus w ord d ifferential analog input range: v ref 0 v to v ref with v ref between 2 .4 v to 5. 1 v single 1.8 v s upply operation with 1.71 v to 5.5 v logic interface sar architecture : n o latency/pipeline delay guaranteed o peration : ?40c to 125 c serial interface spi - /qspi - /microwire - /dsp - compatible ability to daisy - chain multiple adcs and busy indicator 10- lead package : 3 mm 3 mm lfcsp and 3 mm 4.90 mm msop applications automatic t est e quipment machine a utomation medical e quipment battery - powered equipment precision d ata acquisition systems general description the ad4003 is a low noise, low power, high speed , 18 - bit, 2 msps precision successive approximation register (sar) analog - to - digital converter (adc) . it incor porates ease of use features that lower the signal chain power, reduc e signal chain complexity , and enable higher channel density. the high - z mode , coupled with a long acquisition phase , eliminates the need for a dedicated high power, high speed adc driver, thus broadening the range of low power pre cision amplifiers that can drive this adc directly , while still achieving optimum performance. the input span compression feature enables the adc driver amplifier and the adc to operate off common supply rails without the need for a negative supply while p reserving the full adc code range. the low serial peripheral interface ( spi ) clock rate requiremen t reduces the digital input/output power consumption, broadens processor options , and simplifies the t ask of sending data across digital isolation. operating from a 1.8 v supply, the ad4003 has a v ref fully differ - ential input range with v ref ranging from 2. 4 v to 5.1 v. the ad4003 consumes only 16 mw at 2 msps with a minimum of 75 mhz sck rate in turbo mode and achieves 1. 0 lsb (3.8 ppm) i nl maximum, guaranteed no missing codes at 18 bits with 100 .5 db typical snr. the reference voltage is applied externally and can be set independent ly of the supply voltage. the spi - compatible versatile serial interface features seven different modes including the ability, using the sdi input, to daisy - chain several adcs on a single 3 - wire bus and provides an optional busy i ndicator. the ad4003 is compatible with 1.8 v, 2.5 v, 3 v, and 5 v logic, using the separate vio supply. the ad4003 is available in a 10 - lead msop or a 10 - lead lfcsp with operati on specified from ?40c to +125c . the device is pin compatible with the 1 6 - bit, 2 msps ad4000 . functional block dia gram 14957-001 gnd in+ in? sdi sck sdo cnv ad4003 18-bit sar adc serial interface vio ref vdd v ref 0 v ref 0 v ref /2 v ref /2 high-z mode clamp span compression turbo mode status bits 2.5v to 5v 1.8v 10f 1.8v to 5v 3-wire or 4-wire spi interface (daisy chain, cs) figure 1 .
ad4003* product page quick links last content update: 11/01/2016 comparable parts view a parametric search of comparable parts evaluation kits ? ad4000/ad4003 evaluation board documentation data sheet ? ad4003: 18-bit, 2 msps precision sar differential adc data sheet user guides ? evaluation board for the ad4000/ad4003 16-/18-bit precision sar adcs software and systems requirements ? ad4000/ad4003 fpga device driver tools and simulations ? ad4000/ad4003 ibis models design resources ? ad4003 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad4003 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
ad4003 data sheet rev. 0 | page 2 of 33 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general desc ription ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifi cations .................................................................. 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 ter mi nolo g y ...................................................................................... 9 typical performanc e characteristics ........................................... 10 theory of operation ...................................................................... 14 circuit information .................................................................... 14 converter operation .................................................................. 14 transfer functions ...................................................................... 15 applications information .............................................................. 16 typical connection diagram ................................................... 16 analog inputs .............................................................................. 17 driver amplifi er choice ........................................................... 19 ease of drive features ............................................................... 19 voltage reference input ............................................................ 21 power supply ............................................................................... 21 digital interfac e .......................................................................... 21 register read/write functionality ........................................... 22 status word ................................................................................. 24 cs mode, 3 - wire tur b o mo d e ................................................. 25 cs mode, 3 - wire without busy indicator ............................. 26 cs mode, 3 - wire with busy indicator .................................... 27 cs mode, 4 - wire tur b o mo d e ................................................. 28 cs mode, 4 - wire without busy indicator ............................. 29 cs mode, 4 - wire wit h busy indicator .................................... 30 daisy - chain mode ..................................................................... 31 layout guidelines ....................................................................... 32 evaluating the ad4003 performance ....................................... 32 outline dimensions ....................................................................... 33 ordering guide .......................................................................... 33 revision history 10/ 2016 revis ion 0 : initial version
data sheet ad4003 rev. 0 | page 3 of 33 specifications vdd = 1.71 v to 1.89 v ; v io = 1. 71 v to 5 .5 v ; v ref = 5 v ; all specifications t min to t max , h igh - z m ode disabled, span compression disabled , a nd turbo mode enabled ( f s = 2 msps) , unless otherwise note d. table 1. parameter test conditions/comments min typ max unit resolution 18 bits analog input voltage range v in+ ? v in? ? v ref + v ref v span c ompression enabled ? v ref 0. 8 + v ref 0. 8 v operating input voltage v in+ , v in? to gnd ?0.1 v ref + 0.1 v span c ompression enabled 0.1 v ref 0.9 v ref v common - mode input range v ref /2 ? 0.125 v ref /2 v ref /2 + 0 .125 v common - mode rejection ratio ( cmrr ) f in = 500 khz 68 db analog input current acquisition phase , t = 25c 0.3 na high - z mode enabled , converting dc input at 2 msps 1 a throughput complete cycle 500 ns conversion time 290 320 ns acquisition phase 1 290 ns throughput rate 2 0 2 msps transient response 3 250 ns dc accuracy no missing codes 18 bits integral linearity error ?1. 0 0. 4 +1. 0 lsb ? 3.8 1. 52 +3.8 ppm differential linearity error ?0.75 0. 3 +0.75 lsb transition noise 0.8 lsb zero error ? 7 + 7 lsb zero error drift 4 ? 0.21 + 0.21 ppm/c gain error ?2 6 3 +2 6 lsb gain error drift 4 ? 1.23 + 1.23 ppm/c power supply sensitivity vdd = 1.8 v 5% 1.5 lsb 1/f noise 5 bandwidth = 0.1 hz to 10 hz 6 v p -p ac accuracy dynamic range 101 db total rms n oise 31.5 v rms f in = 1 khz, ?0.5 dbfs, v ref = 5 v signal -to - noise ratio (snr) 99 100.5 db spurious - free dynamic range (sfdr) 122 db total harmonic distortion (thd) ?123 db signal -to - noise -and - distortion ratio (sinad) 98.5 100 db oversampled dynamic range oversampling ratio (osr) = 256, v ref = 5 v 122 db f in = 1 khz, ?0.5 dbfs, v ref = 2.5 v snr 93.5 94.5 db sfdr 122 db thd ?119 db sinad 93 94 db
ad4003 data sheet rev. 0 | page 4 of 33 parameter test conditions/comments min typ max unit f in = 100 khz, ?0.5 dbfs, v ref = 5 v snr 99 db thd ?100 db sinad 96.5 db f in = 400 khz, ?0.5 dbfs, v ref = 5 v snr 91.5 db thd ?94 db sinad 90 db ?3 db input bandwidth 10 mhz aperture delay 1 ns aperture jitter 1 ps rms reference voltage range (v ref ) 2.4 5.1 v current 2 msps, v ref = 5 v 1.1 ma overvoltage clamp i in+ /i in? v ref = 5 v 50 ma v ref = 2.5 v 50 ma v in+ /v in? at maximum i in+ /i in? v ref = 5 v 5.4 v v ref = 2.5 v 3.1 v v in+ /v in? clamp on/off threshold v ref = 5 v 5.25 5.4 v v ref = 2.5 v 2.68 2.8 v deactivation time 360 ns ref current at maximum i in+ /i in? v in+ /v in? > v ref 100 a digital inputs logic levels input low voltage, v il vio > 2.7 v ?0.3 +0.3 vio v vio 2.7 v ?0.3 +0.2 vio v input high voltage, v ih vio > 2.7 v 0.7 vio vio + 0.3 v vio 2.7 v 0.8 vio vio + 0.3 v input low current, i il ?1 +1 a input high current, i ih ?1 +1 a input pin capacitance 6 pf digital outputs data format serial 18 bits, twos complement pipeline delay conversion results available immediately after completed conversion output low voltage, v ol i sink = 500 a 0.4 v output high voltage, v oh i source = ?500 a vio ? 0.3 v power supplies vdd 1.71 1.8 1.89 v vio 1.71 5.5 v standby current vdd = 1.8 v, vio = 1.8 v, t = 25c 1.6 a power dissipation vdd = 1.8 v, vio = 1.8 v, v ref = 5 v 10 ksps, high - z mode disabled 80 w 1 msps, high - z mode disabled 8 mw 2 msps, high - z mode disabled 16 18.5 mw 1 msps, high - z mode enabled 10 mw 2 msps, high - z mode enabled 20 24.5 mw vdd only 2 msps, high - z mode disabled 9.5 mw ref only 2 msps, high - z mode disabled 5.5 mw
data sheet ad4003 rev. 0 | page 5 of 33 parameter test conditions/comments min typ max unit vio only 2 msps, high - z mode disabled 1.0 mw energy per conversion 8 nj/sample temperature range specified performance t min to t max ?40 +125 c 1 the acquisition phase is the t ime available for the input sampling capacitors to acquire a new input with the adc running at a throughput rate of 2 msps . 2 a throughput rate of 2 msps can only be achieved with turbo mode enabled and a minimum sck rate of 75 mhz. refer to table 4 for the maximum achievable throughput for different modes of operation. 3 transient response is the time required for the adc to acquire a full - scale input step to 1 lsb accuracy. 4 the minimum and maximum values are guaranteed by characterization , not production tested. 5 see the 1/f noise plot in figure 18. timing specification s vdd = 1.71 v to 1.89 v ; vio = 1.71 v to 5.5 v; v ref = 5 v; all specifications t min to t max , high - z mode disabled, span compression disabled , and turbo mode enabled ( f s = 2 msps ) , unless otherwise note d . 1 table 2. digital interface timing parameter symbol min typ max unit conversion time cnv rising edge to data available t conv 290 320 ns acquisition phase 2 t acq 290 ns time between conversions t cyc 500 ns cnv pulse width ( cs mode) 3 t cnvh 10 ns sck period ( cs mode) 4 t sck vio > 2.7 v 9.8 ns vio > 1.7 v 12.3 ns sck period ( daisy - chain mode) 5 t sck vio > 2.7 v 20 ns vio > 1.7 v 25 ns sck low time t sckl 3 ns sck high time t sckh 3 ns sck falling edge to data remains valid delay t hsdo 1.5 ns sck falling edge to data valid delay t dsdo vio > 2.7 v 7.5 ns vio > 1.7 v 10.5 ns cnv or sdi low to sdo d1 7 msb valid delay ( cs mode) t en vio > 2.7 v 10 ns vio > 1.7 v 13 ns cnv rising edge to first sck rising edge d elay t quiet1 190 ns last sck falling e dge to cnv rising edge d elay 6 t quiet2 60 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode) t dis 20 ns sdi valid setup time from cnv rising edge t ssdicnv 2 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 2 ns sck valid hold time from cnv rising edge ( daisy - chain mode) t hsckcnv 12 ns sdi valid setup time from sck rising edge ( daisy - chain mode) t ssdisck 2 ns sdi valid hold time from sck rising edge ( daisy - chain mode) t hsdisck 2 ns 1 see figure 2 for the timing voltage levels. 2 the acquisition phase is the t ime available for the input sampling capacitors to acquire a new input with the adc running at a throughput rate of 2 msps . 3 for turbo mode, t cnvh must match the t quiet1 minimum. 4 a throughput rate of 2 msps can only be ach ieved with turbo mode enabled and a minimum sck rate of 75 mhz. 5 a 50% duty cycle is assumed for sck. 6 see figure 22 for sinad vs. t quiet2 .
ad4003 data sheet rev. 0 | page 6 of 33 table 3. register read/write timing parameter symbol min typ max unit read/write operation cnv pulse width 1 t cnvh 10 ns sck period t sck vio > 2.7 v 9.8 ns vio > 1.7 v 12.3 ns sck low time t sckl 3 ns sck high time t sckh 3 ns read operation cnv low to sdo d1 7 msb valid delay t en vio > 2.7 v 10 ns vio > 1.7 v 13 ns sck falling edge to data remains valid t hsdo 1.5 ns sck falling edge to data valid delay t dsdo vio > 2.7 v 7.5 ns vio > 1.7 v 10.5 ns cnv r ising e dge to sdo high impedance t dis 20 n s write operation sdi valid setup time from sck rising edge t ssdisck 2 n s sdi valid hold time from sck rising edge t hsdisck 2 n s cnv rising edge to sck e dge hold time t hcnvsck 0 n s cnv falling edge to sck active edge setup time t scnvsck 6 n s 1 for turbo mode, t cnvh must match the t quiet1 minimum. x% vio 1 y% vio 1 v ih 2 v il 2 v il 2 v ih 2 t delay t delay 1 for vio 2.7v, x = 80, and y = 20; for vio > 2.7v, x = 70, and y = 30. 2 minimum v ih and maximum v il used. see digital inputs specifications in table 1. 14957-002 figure 2 . voltage levels for timing table 4 . achievable throughput for different modes of operation parameter test conditions/comments min typ max unit throughput , cs mode 3- wire and 4 - wire turbo mode f sck = 100 mhz, vio 2.7 v 2 msps f sck = 80 mhz, vio < 2.7 v 2 msps 3- wire and 4 - wire turbo mode and six status bits f sck = 100 mhz, vio 2.7 v 2 msps f sck = 80 mhz, vio < 2.7 v 1.78 msps 3- wire and 4 - wire mode f sck = 100 mhz, vio 2.7 v 1.75 msps f sck = 80 mhz, vio < 2.7 v 1.62 msps 3- wire and 4 - wire mode and six status bits f sck = 100 mhz, vio 2.7 v 1.59 msps f sck = 80 mhz, vio < 2.7 v 1.44 msps
data sheet ad4003 rev. 0 | page 7 of 33 absolute maximum rat ings table 5. parameter rating analog inputs in+, in? to gnd 1 ?0.3 v to v ref + 0. 4 v or 50 ma supply voltage ref , vio to gnd ?0.3 v to +6.0 v vdd to gnd ?0.3 v to + 2.1 v vdd to vio ?6 v to +2.4 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c lead temperature soldering 260c reflow as per jedec j - std -020 esd ratings human body model 4 kv machine model 200 v field - induced charged device model 1.25 kv 1 see the analog inputs section for an explanation of in+ and in?. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. t his is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. note that the clamp cannot sustain the overvoltage condition for an indefinite time. thermal resistance t hermal performance is directly linked to printed circuit board (pcb) design and operating environment. careful attenti on to pcb thermal design is required. table 6. thermal resistance package type ja j c unit rm -10 1 147 38 c/w cp - 10 - 9 1 114 33 c/w 1 test condition 1: thermal impedance simulated values are based upon use of 2s2p jedec pcb. see the ordering guide . esd caution
ad4003 data sheet rev. 0 | page 8 of 33 pin configurations and function descriptions ref 1 vdd 2 in+ 3 in? 4 gnd 5 vio 10 sdi 9 sck 8 sdo 7 cnv 6 ad4003 top view (not to scale) 14957-003 figure 3. 10-lead ms op pin configuration 1 ref 2 vdd 3 in+ 4 in? 5 gnd 10 vio 9sdi 8sck 7sdo 6 cnv ad4003 top view (not to scale) 14957-004 notes 1. connect the exposed pad to gnd. this connection is not required to meet the specified perform ance. figure 4. 10-lead lfcsp pin configuration table 7. pin function descriptions pin no. mnemonic type 1 description 1 ref ai reference input voltage. the v ref range is 2.4 v to 5.1 v. this pin is referred to the gnd pin and must be decoupled closely to the gnd pin wi th a 10 f x7r ceramic capacitor. 2 vdd p 1.8 v power supply. the range of vdd is 1.71 v to 1.89 v. bypass vdd to gnd with a 0.1 f ceramic capacitor. 3 in+ ai differential positive analog input. 4 in? ai differential negative analog input. 5 gnd p power supply ground. 6 cnv di convert input. this input has multiple functions. on its leading edge, it initiates the conversions and selects the interface mode of the device: daisy-chain mode or cs mode. in cs mode, the sdo pin is enabled when cnv is low. in daisy-chain mode, th e data is read when cnv is high. 7 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 8 sck di serial data clock input. when the device is selected, the conversion result is shifted out by this clock. 9 sdi di serial data input. this input provides multiple features. it selects the interface mode of the adc as follows. chain mode is selected if sdi is low during the cnv risi ng edge. in this mode, sdi is used as a data input to daisy-chain the conversion results of two or more adcs on to a single sdo line. the digital data level on sdi is output on sdo with a delay of 18 sck cycles. cs mode is selected if sdi is high during the cnv rising edge. in this mode, either sdi or cnv can enab le the serial output signals when low. if sdi or cnv is low when the conversion is complete, the busy indicator feature is enabled. with cnv low, the device can be programmed by clocking in a 16-bit word on sdi on the rising edge of sck. 10 vio p input/output interface digital power. nominally at the same supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v). bypass vio to gnd with a 0.1 f ceramic capacitor. n/a 2 epad p exposed pad (lfcsp only). connect the exposed pad to gnd. this connection is not required to meet the specified performance. 1 ai is analog input, p is power, di is digital input, and do is digital output. 2 n/a means not applicable.
data sheet ad4003 rev. 0 | page 9 of 33 terminology integral nonlinearity error (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? ls b beyond the last code transition. the deviation is measured from the middle of each code to the true straight line (see figure 30). differential non linearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. zero error zero error is the difference bet ween the ideal midscale voltage, that is, 0 v, from the actual voltage producing the midscale output code, that is, 0 lsb. gain error the first transition (from 100 ... 00 to 100 ... 01) occur s at a level ? lsb above nominal negative full scale (?4.999981 v for the 5 v range). the last transition (from 011 10 to 011 11) occur s for an analog voltage 1? lsb below the nominal full scale (+4.999943 v for the 5 v range). the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad as follows : enob = ( sinad db ? 1.76)/6.02 enob is expressed in bits. noise free code resolution noise free code resolution is the number o f bits beyond which it is impossible to distinctly resolve individual codes. it is calculated as noise free code resolution = log 2 (2 n / peak - to - peak noise ) noise free code resolution is expressed in bits. effective resolution effective resolution is calculated as effective resolution = log 2 (2 n / rms input noise ) effective resolution is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expressed in decibels. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured. the value for dynamic range is expressed in decibels. it is measured with a signal at ?60 dbf s so that it includes all n oise sources and dnl artifacts. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal -to - noise - and - distortion ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the nyquist frequency, including harmonics but excluding dc. the v alue of sinad is expressed in decibels. aperture delay aperture delay is the measure of the acquisition performance and is the time between the rising edge of the cnv input and when the input signal is held for a conversion. transient response transient re sponse is the time required for the adc to to acquire a full - scale input step to 1 lsb accuracy . c ommon -m ode rejection ratio ( cm rr) cmrr is the ratio of the power in the adc output at the frequency, f, to the power of a 200 mv p - p sine wave applied to the common - mode voltage of in+ and in? of frequency, f. cmrr (db) = 10log( p adc_in / p adc_out ) where: p adc_in is the common - mode power at the frequency, f, applied to the in+ and in ? inputs. p adc_out is the power at the frequency, f, in the adc output. power su pply rejection ratio (psrr) psrr is the ratio of the power in the adc output at the frequency, f, to the power of a 200 mv p - p sine wave applied to the adc vdd supply of frequency , f. psrr (db) = 10 log( p vdd_in / p adc_out ) where: p vdd_in is the power at the frequency, f, at the vdd pin. p adc_out is the power at the frequency, f, in the adc output.
ad4003 data sheet rev. 0 | page 10 of 33 typical performance characteristics vdd = 1.8 v; vio = 3.3 v; v ref = 5 v; t = 25c, high-z mode disabled, span compression disabled and turbo mode enabled (f s = 2 msps), unless otherwise noted. 1.0 0.8 0.4 0 0.6 0.2 ?0.2 ?0.6 ?0.4 ?0.8 ?1.0 0 32768 65536 131072 196608 98304 163840 229376 262144 inl (lsb) code +125c +25c ?40c 14957-200 figure 5. inl vs. code and temperature, v ref = 5 v 1.0 0.8 0.4 0 0.6 0.2 ?0.2 ?0.6 ?0.4 ?0.8 ?1.0 inl (lsb) +125c +25c ?40c 0 32768 65536 131072 196608 98304 163840 229376 262144 code 14957-201 figure 6. inl vs. code and temperature, v ref = 2.5 v 0.8 0.6 0 0.4 0.2 ?0.2 ?0.6 ?0.4 ?0.8 inl (lsb) high-z enabled span compression enabled 0 32768 65536 131072 196608 98304 163840 229376 262144 code 14957-202 figure 7. inl vs. code, high-z and span compression modes enabled, v ref = 5 v 0.4 0 0.3 0.2 0.1 ?0.1 ?0.3 ?0.2 ?0.4 dnl (lsb) +125c +25c ?40c 0 32768 65536 131072 196608 98304 163840 229376 262144 code 14957-203 figure 8. dnl vs. code and temperature, v ref = 5 v 0.4 0 0.3 0.2 0.1 ?0.1 ?0.3 ?0.2 ?0.4 dnl (lsb) +125c +25c ?40c 0 32768 65536 131072 196608 98304 163840 229376 262144 code 14957-204 figure 9. dnl vs. code and temperature, v ref = 2.5 v 1.8 1.5 0.9 1.1 1.7 1.3 1.4 1.0 1.6 1.2 0.8 transition noise (lsb) 2.5 4.5 4.0 3.5 3.0 5.0 reference voltage (v) +125c +25c ?40c 14957-206 figure 10. transition noise vs. reference voltage
data sheet ad4003 rev. 0 | page 11 of 33 4.5m 2.0m 3.5m 4.0m 3.0m 2.5m 1.5m 0.5m 1.0m 0 131062 131064 131068 131072 131066 131070 131076 131077 131081 131074 131079 131063 131067 131071 131065 131069 131075 131080 131073 131078 dnl (lsb) code v ref = 2.5v v ref = 5v 14957-205 figure 11 . histogram of a dc input at code center, v ref = 2.5 v, 5 v 0 ?60 ?160 ?120 ?20 ?100 ?80 ?140 ?40 ?180 fundamental amplitude (db) 100 100k 10k 1k 1m frequency (hz) v ref = 5v snr = 100.33db thd = ?123.99db sinad = 100.31db 14957-207 figure 12 . 1 khz, 0.5 dbfs input tone fft, wide view , v ref = 5 v 0 ?60 ?160 ?120 ?20 ?100 ?80 ?140 ?40 ?180 fundamental amplitude (db) 1k 100k 10k 1m frequency (hz) v ref = 5v snr = 98.37db thd = ?98.52db sinad = 95.58db 14957-210 figure 13 . 100 khz, 0.5 dbfs input tone fft, wide view 4.5m 2.0m 3.5m 4.0m 3.0m 2.5m 1.5m 0.5m 1.0m 0 131062 131064 131068 131072 131066 131070 131076 131077 131081 131074 131079 131063 131067 131071 131065 131069 131075 131080 131073 131078 dnl (lsb) code v ref = 2.5v v ref = 5v 14957-208 figure 14 . histogram of a dc input at code transition, v ref = 2.5 v, 5 v 0 ?60 ?160 ?120 ?20 ?100 ?80 ?140 ?40 ?180 fundamental amplitude (db) 100 100k 10k 1k 1m frequency (hz) v ref = 2.5v snr = 95.01db thd = ?118.60db sinad = 94.99db 14957-209 figure 15 . 1 khz, 0.5 dbfs input tone fft, wide view, v ref = 2.5 v 0 ?60 ?160 ?120 ?20 ?100 ?80 ?140 ?40 ?180 fundamental amplitude (db) 1k 100k 10k 1m frequency (hz) v ref = 5v snr = 91.22db thd = ?91.97db sinad = 89.15db 14957-213 figure 16 . 400 khz, 0.5 dbfs input tone fft, wide view
ad4003 data sheet rev. 0 | page 12 of 33 102 97 99 100 101 98 95 96 94 16.6 15.4 15.6 15.8 16.0 16.2 16.4 snr, sinad (db) enob (bits) 2.4 4.8 4.5 3.9 4.2 3.6 3.3 3.0 2.7 5.1 reference voltage (v) enob sinad snr 14957-219 figure 17 . snr, sinad, and enob vs. reference voltage 60 58 55 56 59 57 54 adc output reading (v) 0 9 8 5 6 7 4 3 2 1 10 time (seconds) 14957-217 figure 18 . 1/f noise for 0.1 hz to 10 hz band width, 50 k sps , 2500 samples averaged per reading 135 130 120 110 125 115 105 100 95 snr (db) 0 2 4 8 16 32 64 128 256 512 1024 2048 decimation rate dynamic range f in = 1khz f in = 10khz 14957-212 figure 19 . snr vs. decimation rate for various input frequencies ?114 ?124 ?120 ?118 ?116 ?122 ?128 ?126 ?130 133 126 127 128 130 129 131 132 thd (db) sfdr (db) 2.4 4.8 4.5 3.9 4.2 3.6 3.3 3.0 2.7 5.1 reference voltage (v) sfdr thd 14957-216 figure 20 . thd and sfdr vs. reference voltage 1.1 0.9 0.6 0.7 1.0 0.8 0.5 0.4 reference current ( ma) 2.4 4.8 4.5 3.9 4.2 3.6 3.3 3.0 2.7 5.1 reference voltage (v) 14957-218 figure 21 . reference current vs. reference voltage 101 100 98 96 99 97 95 sinad (db) 0 10 20 30 40 50 60 70 80 t quiet2 (ns) vio = 1.89v vio = 3.6v vio = 5.5v 14957-215 figure 22 . sinad vs. t quiet2
data sheet ad4003 rev. 0 | page 13 of 33 100.8 100.0 100.4 100.6 100.2 99.6 99.8 99.4 16.42 16.22 16.24 16.26 16.28 16.30 16.32 16.34 16.36 16.38 16.40 snr, sinad (db) enob (bits) ?40 100 80604020 0 ?20 120 temperature (c) enob sinad snr 14957-222 figure 23. snr, sinad, and enob vs. temperature, f in = 1 khz 8 7 3 5 6 4 1 2 0 operating current (ma) vdd high-z disabled vdd high-z enabled ref high-z disabled ref high-z enabled vio high-z disabled vio high-z enabled ?40 100 80 6040 20 0 ?20 120 temperature (c) 14957-223 figure 24. operating currents vs. temperature 10 ?4 4 8 0 2 6 ?2 ?8 ?6 ?10 zero error and gain error (lsb) ?40 100 80604020 0 ?20 120 temperature (c) pfs gain error nfs gain error zero error 14957-221 figure 25. zero error and gain error vs. temperature (pfs is positive full scale and nfs is negative full scale) ? 114.0 ?114.5 ?116.5 ?115.5 ?115.0 ?116.0 ?117.0 ?117.5 118.0 117.9 117.4 117.7 117.8 117.6 117.2 117.3 117.5 117.1 117.0 thd (db) sfdr (db) ?40 100 80604020 0 ?20 120 temperature (c) thd sfdr 14957-225 figure 26. thd and sfdr vs. temperature, f in = 1 khz 25.0 20.0 10.0 15.0 5.0 22.5 17.5 7.5 12.5 2.5 0 standby current (a) ?40 100 80604020 0 ?20 120 temperature (c) 14957-226 figure 27. standby current vs. temperature 23 21 13 17 19 15 9 11 7 5 t dsdo (ns) 01 0 0 806040 200180160 140 20 220 120 load capacitance (pf) vio = 5v vio = 3.3v vio = 1.8v 14957-224 figure 28. t dsdo vs. load capacitance
ad4003 data sheet rev. 0 | page 14 of 33 theory of operation comp control logic switches control busy output code cnv c c 2c 65,536c 4c 131,072c lsb sw+ msb lsb sw? msb c c 2c 65,536c 4c 131,072c in+ ref g nd in? 14957-007 figure 29. adc simplified schematic circuit information the ad4003 is a high speed, low power, single-supply, precise, 18-bit adc based on a sar architecture. the ad4003 is capable of converting 2,000,000 samples per second (2 msps) and powers down between conversions. when operating at 10 ksps, for example, it typically consumes 80 w, making it ideal for battery-powered applications because its power scales linearly with throughput. the ad4003 has a valid first conversion after being powered down for long periods. the ad4003 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiplexed applications. the ad4003 incorporates a multitude of unique ease of use features that result in a lower system power and footprint. the ad4003 has an internal voltage clamp that protects the device from overvoltage damage on the analog inputs. the analog input incorporates circuitry that reduces the nonlinear charge kickback seen from a typical switched capacitor sar input. this reduction in kickback, combined with a longer acquisition phase, means reduced settling requirements on the driving amplifier. this combination allows the use of lower bandwidth and lower power amplifiers as drivers. it has the additional benefit of allowing a larger resistor value in the input rc filter and a corresponding smaller capacitor, which results in a smaller rc load for the amplifier, improving stability and power dissipation. high-z mode can be enabled via the spi interface by programming a register bit (see table 14). when high-z mode is enabled, the adc input has low input charging current at low input signal frequencies as well as improved distortion over a wide frequency range up to 100 khz. for frequencies above 100 khz and multiplexing, disable high-z mode. for single-supply applications, a span compression feature creates additional headroom and footroom for the driving amplifier to access the full range of the adc. the fast conversion time of the ad4003 , along with turbo mode, allows low clock rates to read back conversions even when running at the full 2 msps throughput rate. note that a throughput rate of 2 msps can be achieved only with turbo mode enabled and a minimum sck rate of 75 mhz. the ad4003 can be interfaced to any 1.8 v to 5 v digital logic family. it is available in a 10-lead msop or a tiny 10-lead lfcsp that allows space savings and flexible configurations. it is pin for pin compatible with the 14-/16-/18-bit precision sar adcs listed in table 8. table 8. msop, lfcsp 14-/16-/18-bit precision sar adcs bits 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps 18 1 ad7989-1 2 ad7691 2 ad7690 , 2 ad7989-5 2 ad4003 , ad7982 , 2 ad7984 2 16 1 ad7684 ad7687 ad7688 , 2 ad7693 2 ad7915 2 16 3 ad7680, ad7683, ad7988-1 2 ad7685 , 2 ad7694 ad7686 , 2 ad7988-5 ad4000 14 3 ad7940 ad7942 2 ad7946 2 ad7980 , 2 ad7983 2 1 true differential. 2 pin for pin compatible. 3 pseudo differential. converter operation the ad4003 is a sar-based adc using a charge redistribution sampling digital-to-analog converter (dac). figure 29 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 18 binary weighted capacitors, which are connected to the comparator inputs. during the acquisition phase, terminals of the array tied to the input of the comparator are connected to gnd via sw+ and sw?. all independent switches connect the other terminal of each capacitor to the analog inputs. therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? inputs.
data sheet ad4003 rev. 0 | page 15 of 33 when the acquisition phase is complete and the cnv input goes high, a conversion phase is initiated. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. the differential voltage between the in+ and in? inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and v ref , the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4, , v ref /262,144). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the control logic generates the adc output code and a busy signal indicator. because the ad4003 has an on-board conversion clock, the serial clock, sck, is not required for the conversion process. transfer functions the ideal transfer characteristics for the ad4003 are shown in figure 30 and table 9. 100...000 100...001 100...010 011...101 011...110 011...111 adc code (twos complement) analog input +fsr ? 1.5 lsb +fsr ? 1 lsb ?fsr + 1 lsb ?fsr ?fsr + 0.5 lsb 14957-008 figure 30. adc ideal transfer func tion (fsr is full-scale range) table 9. output codes and ideal input voltages description analog input, v ref = 5 v v ref = 5 v with span compression enabled digital output code (hex) fsr ? 1 lsb +4.999962 v +3.999969 v 0x1ffff 1 midscale + 1 lsb +38.15 v +30.5 v 0x00001 midscale 0 v 0 v 0x00000 midscale ? 1 lsb ?38.15 v ?30.5 v 0x3ffff ?fsr + 1 lsb ?4.999962 v ?3.999969 v 0x20001 ?fsr ?5 v ?4 v 0x20000 2 1 this output code is also the code for an overranged analog input (v in+ ? v in? above v ref ). 2 this output code is also the code for an underranged analog input (v in+ ? v in? below ?v ref ).
ad4003 data sheet rev. 0 | page 16 of 33 applications information typical application diagrams figure 31 shows an example of the recommended connection diagram for the ad4003 when multiple supplies are available. this configuration is used for best performance because the amplifier supplies can be selected to allow the maximum signal range. figure 32 shows a recommended connection diagram when using a single-supply system. this setup is preferable when only a limited number of rails are available in the system and power dissipation is of critical importance. figure 33 shows a recommended connection diagram when using a fully differential amplifier. c r v+ ref vdd vio gnd in+ in? sdi sck sdo cnv ad4003 3-wire/4-wire interface 1.8v 1.8v to 5v v + +6.5 v digital host (microprocessor/ fpga) v? ?0.5v host supply 0.1f 0.1f 5v c r v? v+ v? amp amp v ref 0v v ref 0v v cm = v ref /2 v cm = v ref /2 ref 1 ldo amp v cm = v ref /2 10f 10k ? 10k ? 14957-009 figure 31. typical application diagram with multiple supplies c r ref vdd vio gnd in+ in? sdi sck sdo cnv ad4003 2 1.8v 1.8v to 5v v +=+5 v digital host (microprocessor/ fpga) host supply 0.1f 0.1f 100nf 100nf 4.096v c r amp amp 0.9 v ref 0.1 v ref 0.9 v ref 0.1 v ref v cm = v ref /2 v cm = v ref /2 ref 1 ldo amp v cm = v ref /2 10f 1 10k ? 10k ? 1 see the voltage reference input section for reference selection. c ref is usually a 10f ceramic capacitor (x7r). 2 span compression mode enabled. 3 see table 9 for rc filter and amplifier selection. 3-wire/4-wire interface 14957-010 3 figure 32. typical application diagram with a single supply
data sheet ad4003 rev. 0 | page 17 of 33 10f ref vdd vio gnd in+ in? sdi sck sdo cnv ad4003 3-wire/4-wire interface 1.8v 1.8v to 5v digital host (microprocessor/ fpga) 4.096v 0.1f v ocm r3 1k ? +in v+ ?in ?out +out r4 1k? 10k ? 10k ? r2 1k? r r differential amplifier r1 1k ? 0.1f v cm = v ref /2 host supply v? c c ref v + = +5v ldo amp v ref 0 v cm = v ref /2 v ref 0 v cm = v ref /2 0.1f 14957-011 v cm = v ref /2 figure 33. typical application diagram with a fully differential amplifier ref vdd vio gnd in+ in? sdi sck sdo cnv ad4003 1.8v to 5v +in ?in r4 1k? differential amplifier r1 1k? v? amp +v ref ?v ref 0v 1.8v 10f r3 1k? v+ ?out +out r2 1k? r r 0.1f vref/2 host supply c c ref v + = +5v ldo 10k ? 10k? v ocm 4.096v 0.1f 0.1f 3-wire/4-wire interface digital host (microprocessor/ fpga) 14957-012 v cm = v ref /2 figure 34. typical application diagram for single-ended to differential conversion with a fully differential amplifier analog inputs figure 35 shows an equivalent circuit of the analog input structure, including the overvoltage clamp of the ad4003. input overvoltage clamp circuit most adc analog inputs, in+ and in?, have no overvoltage protection circuitry apart from esd protection diodes. during an overvoltage event, an esd protection diode from an analog input (in+ or in?) pin to ref forward biases and shorts the input pin to ref, potentially overloading the reference or causing damage to the device. the ad4003 internal overvoltage clamp circuit with a larger external resistor (r ext = 200 ) eliminates the need for external protection diodes and protects the adc inputs against dc overvoltages. in applications where the amplifier rails are greater than v ref and less than ground, it is possible for the output to exceed the input voltage range of the device. in this case, the ad4003 internal voltage clamp circuit ensures that the voltage on the input pin does not exceed v ref + 0.4 v and prevents damage to the device by clamping the input voltage in a safe operating range and avoiding disturbance of the reference; this is particularly important for systems that share the reference among multiple adcs. if the analog input exceeds the reference voltage by 0.4 v, the internal clamp circuit turns on and the current flows through the clamp into ground, preventing the input from rising further and potentially causing damage to the device. the clamp turns on before d1 (see figure 35) and can sink up to 50 ma of current.
ad4003 data sheet rev. 0 | page 18 of 33 when the clamp is active, it sets the ov clamp flag bit in the register that can be read back (see table 14), which is a sticky bit that must be read to be cleared. the status of the clamp can also be checked in the status bits using an overvoltage clamp flag (see table 15). the clamp circuit does not dissipate static power in the off state. note that the clamp cannot sustain the overvoltage condition for an indefinite time. the external rc filter is usually present at the adc input to band limit the input signal. during an overvoltage event, excessive voltage is dropped across r ext and r ext becomes part of a protection circuit. the r ext value can vary from 200 to 20 k for 15 v protection. the c ext value can be as low as 100 pf for correct operation of the clamp. see table 1 for input overvoltage clamp specifications. 14957-013 c ext r ext v in ref d1 in+/in? gnd clamp 0v to 15v r in c in d2 c pin figure 35. equivalent analog input circuit differential input considerations the analog input structure allows the sampling of the true differential signal between in+ and in?. by using these differential inputs, signals common to both inputs are rejected. figure 36 shows the common-mode rejection capability of the ad4003 over frequency. it is important to note that the differential input signals must be truly antiphase in nature, 180 out of phase, which is required to keep the common-mode voltage of the input signal within the specified range around v ref /2 shown in table 1. 72 71 70 69 68 67 66 cmrr (db) 100 1k 10k 100k 1m frequency (hz) 14957-303 figure 36. common-mode rejection ra tio vs. frequency, vio = 3.3 v, v ref = 5 v, 25c switched capacitor input during the acquisition phase, the impedance of the analog inputs (in+ or in?) can be modeled as a parallel combination of capacitor c pin and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 400 and is a lumped component composed of serial resistors and the on resistance of the switches. c in is typically 40 pf and is mainly the adc sampling capacitor. during the conversion phase, where the switches are open, the input impedance is limited to c pin . r in and c in make a single- pole, low-pass filter that reduces undesirable aliasing effects and limits noise. rc filter values the value of the rc filter and driving amplifier can be selected depending on the input signal bandwidth of interest at the full 2 msps throughput. lower input signal bandwidth means that the rc cutoff can be lower, thereby reducing noise into the converter. for optimum performance at various throughputs, use the recommended rc values (200 , 180 pf) and the ada4807-1 . the rc values in table 10 are chosen for ease of drive considera- tions and also greater adc input protection. the combination of a large r value (200 ) and small c value result in a reduced dynamic load for the amplifier to drive. the smaller value of c means less stability/ phase margin concerns with the amplifier. the large value of r limits the current into the adc input when the amplifier output exceeds the adc input range. table 10. rc filter and amplifier selection for various input bandwidths input signal bandwidth (khz) r () c (pf) recommended amplifier recommended fully differential amplifier <10 see the high-z mode section ada4940-1 <200 200 180 ada4807-1 ada4940-1 >200 200 120 ada4897-1 ada4932-1 multiplexed 200 120 ada4897-1 ada4932-1
data sheet ad4003 rev. 0 | page 19 of 33 driver amplifier choice although the ad4003 is easy to drive, the driver amplifier must meet the following requirements: ? the noise generated by the driver amplifier must be kept low enough to preserve the snr and transition noise perfor- mance of the ad4003 . the noise from the driver is filtered by the single-pole, low-pass filter of the ad4003 analog input circuit made by r in and c in , or by the external filter, if one is used. because the typical noise of the ad4003 is 31.5 v rms, the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 )( 2 31.5 31.5 log20 n db3 loss nef snr where: f ?3 db is the input bandwidth, in megahertz, of the ad4003 (10 mhz) or the cutoff frequency of the input filter, if one is used. n is the noise gain of the amplifier (for example, 1 in buffer configuration). e n is the equivalent input noise voltage of the op amp in nv/hz. ? for ac applications, the driver must have a thd perfor- mance commensurate with the ad4003. ? for multichannel multiplexed applications, the driver amplifier and the ad4003 analog input circuit must settle for a full-scale step onto the capacitor array at an 18-bit level (0.000384%, 3.84 ppm). in the data sheet of the amplifier, settling at 0.1% to 0.01% is more commonly specified. this may differ significantly from the settling time at an 18-bit level and must be verified prior to driver selection. single to differential driver for applications using a single-ended analog signal, either bipolar or unipolar, the ada4940-1 single-ended to differential driver allows a differential input to the device. the schematic is shown in figure 34. high frequency input signals the ad4003 ac performance over a wide input frequency range is shown in figure 37. unlike other traditional sar adcs, the ad4003 ac performance holds up to the nyquist frequency. 102 96 90 100 92 94 98 88 17.0 15.5 16.5 14.5 15.0 16.0 14.0 snr, sinad (db) enob (bits) 1k 100k 10k 1m input frequency (hz) enob sinad snr 14957-211 figure 37. snr, sinad, and enob vs. input frequency ? 90 ?105 ?95 ?115 ?110 ?100 ?120 120 105 115 95 100 110 90 thd (db) sfdr (db) 1k 100k 10k 1m input frequency (hz) thd sfdr 14957-214 figure 38. thd and sfdr vs. input frequency ease of drive features input span compression in single-supply applications, it is desirable to use the full range of the adc; however, the amplifier can have some headroom and footroom requirements, which can be a problem, even if it is a rail-to-rail input and output amplifier. the use of span compression increases the headroom and footroom available to the amplifier by reducing the input range by 10% from the top and bottom of the range while still accessing all available adc codes (see figure 39). the snr decreases by approximately 1.9 db (20 log(8/10)) for the reduced input range when span compression is enabled. span compression is disabled by default, but can be enabled by writing to the relevant register bit (see the digital interface section). 14957-300 adc v ref = 4.096v digital output all 2 n codes +fsr ?fsr 90% of v ref = 3.69 v 10% of v ref = 0.41v a nalo g input 5v in+ figure 39. span compression
ad4003 data sheet rev. 0 | page 20 of 33 high - z m ode the ad4003 incorporates high - z mode , which redu c es the non linear charge kickback when the capacitor dac switches back to the input at the start of acquisition. figure 40 shows t he input current of the ad4003 with h igh - z mode enabled and disabled. the low input current makes the adc easier to drive than the traditional sar adcs available in the market , even with high - z mo de disabled. the input current reduces further to sub microampere range when high - z mode is enabled. the high - z mode is disabled by default, but can be enabled by writing to the register (see tabl e 14 ). disable high - z mode for input frequencies above 100 khz or multiplexing. 15 6 ?12 ?6 12 0 3 ?9 9 ?3 ?15 input current (a) ?5 3 1 ?1 ?3 5 2 0 ?2 ?4 4 input differential voltage (v) 14957-301 25c high-z enabled 25c high-z disabled figure 40 . input current vs . input differential voltage , vio = 3.3 v, v ref = 5 v s ystem designers looking to achieve the optimum data sheet performance from hig h resolution precision sar adcs are ofte n forced to use a dedicated high power, high speed amplifier to drive the traditional switched capacitor sar adc inputs for their precision applications , which is one of the common pain points encountered in designing a precision data acquisition signal chain. the benefits of high - z mode are low input current for slow (<10 k hz) or dc type signals and improved distortion (thd) performance over a frequency up to 100 khz. high - z mode allows a choice of lower power and bandwidth precision amplifiers with a lower rc filter cutoff to drive the adc , removing the need for dedicated high speed adc drivers, which sav es system power, size , and cost in precision, low bandwidth application s. high - z mode allows the amplifier and rc filter in front of the adc to be chosen based on the signal bandwidth of interest and not based on the settling requirements of the switched capacitor sar adc inputs. additionally , the ad4003 can be driven with a much higher source impedance than traditional sars , which means the resist or in the rc filter can have a value 10 times larger than previous sar designs and , with h igh - z mode enabled , can tolerat e even larger impedance. figure 40 shows the thd performance for various source impedances with high - z mode disabled and enabled. figure 42 and figure 43 show the ad4003 snr and thd perfor - mance using the ada4077 - 1 (i quiescent = 400 a/amplifier) an d ada4610 - 1 ( i quiescent = 1.5 ma/amplifier) precision amplifiers when driving the ad4003 at the full throughput of 2 msps for h igh - z mode enabled and disabled with various rc filter values. these amplifiers achieve 96 db to 99 db typical snr and better than ? 110 db thd with high - z enabled. thd is approximately 10 db better with high - z mode enabled , even for large r values. snr holds up close to 99 db , even with a very low rc bandwidth cutoff. ?85 ?90 ?100 ?110 ?95 ?105 ?115 ?120 ?125 thd (db) 1 10 20 input frequency (khz) 1k ? high-z disabled 1k ? high-z enabled 510 ? high-z disabled 510 ? high-z enabled 150 ? high-z disabled 150 ? high-z enabled 14957-228 figure 41 . thd vs . input frequency for various source im pedance, v ref = 5 v when high - z mode is enabled, the adc consume s approximately 2 mw /msps extra power; however, this is still significantly lower than using dedicated adc drivers like the ada4807 - 1 . for any system, the front end usually limits the overall ac/dc performance of the signal chain. it i s evident from the data sheet of the selected precision amplifier s shown in figure 42 and figure 43 that their own noise and distortion performance dominates the snr and thd specification at a certain input frequency. 100 97 91 85 94 88 82 76 79 73 70 260khz 1.3k ? 470pf 498khz 680 ? 470pf 2.27mhz 390 ? 180pf 1.3mhz 680 ? 180pf 4.42mhz 200 ? 180pf snr (db) rc filter bandwidth (hz) resistor (), capacitor (pf) ada4077-1 high-z disabled ada4077-1 high-z enabled ada4610-1 high-z disabled ada4610-1 high-z enabled 14957-227 f igure 42 . snr vs. rc filter bandwidth for v arious precision adc drivers, v ref = 5 v, f in = 1 khz (turbo mode o n , high - z e nabled/ d isabled)
data sheet ad4003 rev. 0 | page 21 of 33 ?80 ?84 ?92 ?100 ?88 ?96 ?104 ?112 ?108 ?116 ?120 thd (db) 260khz 1.3k ? 470pf 498khz 680 ? 470pf 2.27mhz 390 ? 180pf 1.3mhz 680 ? 180pf 4.42mhz 200 ? 180pf rc filter bandwidth (hz) resistor (), capacitor (pf) ada4077-1 high-z disabled ada4077-1 high-z enabled ada4610-1 high-z disabled ada4610-1 high-z enabled 14957-229 figure 43 . thd vs. rc filter bandwidth for v arious precision adc drivers, v ref = 5 v, f in = 1 khz (turbo mode o n , high - z e nabled/ d isabled) long acquisition phase the ad4003 also features a very fast conversion time of 2 9 0 ns , which r esults in a long acquisit ion phase . the acquisition is further extended by a key feature of the ad4003 ; th e adc r eturn s back to the acquisition phase typic ally 100 ns b efore the end of the conversion . this feature provides an even longer time for the adc to acquire the new input voltage. a longer acquisition phase reduces the settling requirement on the driving amplifier , and a lower power/bandwidth amplifier can be chosen. the longer acquis ition phase means that a lower rc filter cutoff can be used , which means a noisier amplifier can also be tolerated. a larger value of r can be used in the rc filter with a correspond ing smaller value of c , reducing amplifier stability concerns without i mpacting distortion performance significantly. a larger value of r also results in reduced dynamic power dissipation in the amplifier. see table 10 for details on se tting the rc filter bandwidth and c hoosing a suitable amplifier. voltage reference in put a 10 f (x7 r, 0 8 0 5 size) ceramic chip capacitor is appropriate for the optimum performance of the reference input . for higher performance and lower drift , use a reference such as the adr4550 . u se a low power reference such as the adr3450 at the expense of a slight decrease in the noise perfo rmance . it is recom mended to use a reference buffer , such as the ada480 7 - 1 , between the refere nce and the adc reference input. it is important to consider the optimum size of capacitance necessary to keep the reference buffer stable as well as to meet the minimum adc requirement stated previously in this section . power supply the ad4003 uses two power supply pins: a core supply (vdd) and a digital input/output interface supply (vio). vio allows direct interface with any logic between 1.8 v and 5.5 v. to reduce the number of supplies needed, vio and vdd can be tied together for 1.8 v opera tion . the adp7118 low noise , cmos , low drop out (ldo) linear regulator is recommended to power the vdd and vio pins . the ad4003 is indep endent of power supply sequencing between vio and vdd. additionally, the ad4003 is insensitive to power supply variations over a wide frequency range, as shown in figure 44. 80 75 70 65 60 55 50 psrr (db) 100 1k 10k 100k 1m frequency (hz) 14957-302 figure 44 . psrr vs . frequency , vio = 3.3 v , v ref = 5 v the ad4003 powers down automatically at the end of each conversion phase; therefore, the power scales linearly with the sampling rate. this feature makes the device ideal for low sampling rates (even of a few hertz) and battery - powered applications. figure 45 shows the ad4003 total power dissipation and individual power dissipation for each rail. 100k 100 10k 1 10 1k 0.1 0.01 power dissipation ( w) 10 1m 100k 10k 1k 100 throughput (hz) vdd vio v ref total power 14957-220 figure 45 . pow er dissipation vs . throughput, vio = 1.8 v , v ref = 5 v digital interface although the ad4003 has a reduced number of pins, it offers flexibility in its serial inte rface modes. the ad4003 can also be programmed via 16 - bit s pi writes to the configuration registers. when in cs mode, the ad4003 is compatible with spi, qspi ? , digital hosts, a nd dsps. in this mode, the ad4003 can use either a 3 - wire or 4 - wire interface. a 3 - wire interface using the cnv, sck, and sdo signals minimizes wiring connect ions , which is useful, for instance, in isolated applications. a 4 - wire interface using the sdi, cnv, sck, and sdo signals allows c nv, which initiates the conversions, to be independent of the readback
ad4003 data sheet rev. 0 | page 22 of 33 timing (sdi). this interface is useful in low jitter sampling or simultaneous sampling applications. t he ad4003 provides a da isy - chain feature using the sdi input for cascading multiple adcs on a single data line similar to a shift register. the mode in which the device operates depends on the sdi level when the cnv rising edge occurs. cs mode is selected if sdi is high, and daisy - chain mode is selected if sdi is low. the sdi hold time is such that when sdi and cnv are connected together, daisy - chain mode is always selected. in either 3 - wire or 4 - wire mode , the ad4003 offers the option of forcing a start bit in front of the data bits. this start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. otherwise, without a busy indicator, the user must ti me out the maximum conversion time prior to readback. the busy indicator feature is enabled i n cs mode if cnv or sdi is low when the adc conversion ends. the state of the sdo on power - up is either low or h igh - z depending on the states of cnv and sdi , as shown in in table 11. table 11 . state of sdo on power -up cnv sdi sdo 0 0 l ow 0 1 hi gh - z 1 0 low 1 1 high - z the ad4003 has turbo mode capability in both 3 - wire and 4 - wire mode. turbo mode is enabled by writing to the configuration register and replaces the busy indicator feature when enable d. tur b o mo d e allows a slower spi clock rate , making interfacing simpler. a throughput rate of 2 msps can be achieved only with turbo mode enabled and a minimum sck rate of 75 mhz . status bits can also be clocked out at the end of the conversion data if the status bits are enable d in the configuration register. there are six status bits in total as described in table 12. the ad4003 is configured by 16 - bit spi writes to the desired configuration register. t he 16 - bit word can be written via the sdi line while cnv is held low . the 16 - bit word consists of an 8 - bit header and 8 - bit register data. f or isolated systems, the adum141d is recommended, which has a max imum clock rate of 75 mhz and allows the ad4003 to run at 2 msps. register read/write functionality the ad4003 register bits are programmable and their default status es are shown in table 12 . the register map is shown in table 14. the overvoltage clamp flag is a read only sticky bit , and it is cleared only if the register is read and the overvoltage condition is no longer pres ent. it gives an indication of overvoltage condition when it i s set to 0. table 12. register bits register bits default status overvoltage ( ov ) c lamp f lag 1 bit (default 1: inactive ) span c ompression 1 bit (default 0 : disable d ) high - z m ode 1 bit (default 0 : disable d ) turbo m ode 1 bit (default 0 : disable d ) enable six s tatus b its 1 bit (default 0 : disable d ) all access to the register map must start with a write to the 8 - b it command register in the spi interface block. the ad4003 ignores all 1 s until the first 0 is clocked in; the value loaded into th e command register is always a 0 followed by seven command bits. this command determines whether that operation is a wr ite or a read. the ad4003 command register is shown in table 13. table 13 . command register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wen r/ w 0 1 0 1 0 0 all register read/writes must occur while cnv is low. data on sdi is clocked in on the rising edge of sck. data on sdo is clocked out on the falling edge of sck. at the end of the data transfer , sdo is put in a high impedance state on the rising edge of cnv if daisy - chain mode is not enable d . if daisy - chain mode is enabled , sdo goes low on the rising edge of cnv. register reads a re not allowed in daisy - chain mode. register write requires three signal lines: sck, cnv, and sdi. during register write, to read the current conversion results on s do, the cnv pin must be brought low after the conversion is completed ; otherwise, the conversion results may be incorrect on sdo, however, the register write occur s regardless . t he lsb of each configuration register is reserved because a user reading 16 - bi t conversion data may be limited to a 16 - bit spi frame. the state of sdi on the last bit in the sdi frame may be the state that then persists as cnv rises. because the state of sdi when cnv rises is part of how the user sets the interface mode, the user in this scenario may need to set the final sdi state on that basis. the timing diagram s in figure 46 through figure 48 show how data is read and written when the ad4003 is configured in register read, w rite , and daisy - chain mode. table 14. register map addr [1:0] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset 0x0 reserved reserved reserved enable six status bits span compression high - z mode turbo mode overv oltage ( ov ) c lamp f lag (read only sticky bit ) 0x e1
data sheet ad4003 rev. 0 | page 23 of 33 t cyc t sck t dis t sck l t sckh t scnvsck t ssdisck t hsdisck t cnvh t en cnv sck 1 2 3 4 5 6 7 0 1 1 0 1 0 1 0 0 b0 b1 b2 b3 b4 b5 b6 wen r/w 0 1 0 1 addr[1:0] 8 9 10 11 12 13 14 15 16 sdi sdo t hsdo t dsdo b7 x d17 d16 d15 d14 d13 d12 d11 d10 14957-021 figure 46 . register read timing diagram 1 conversion result on d17:0 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t cyc t sck t sck l t sckh t scnvsck t ssdisck t hsdisck t cnvh 1 t en cnv sck 1 2 3 4 5 6 7 0 0 1 0 1 0 1 0 0 wen r/w 0 1 0 1 addr[1:0] 8 9 10 11 12 13 14 15 16 17 18 sdi sdo b0 b1 b2 b3 b4 b5 b6 b7 t hsdo t dsdo t hcnvsck 1 the user must wait t conv time when reading back the conversion result and doing a register write at the same time. 14957-022 figure 47 . register write timing diagram sdi a sdo a /sdi b sdo b 0 0 command (0x14) 0 0 command (0x14) 0 0 command (0x14) t cyc t sck t sck l t sckh t scnvsck cnv sck 1 24 t dis t cnvh data (0xab) data (0xab) 14957-023 figure 48 . register w rite timing diagram , d aisy - c hain m ode
ad4003 data sheet rev. 0 | page 24 of 33 status word the 6 - bit status word can be appended to the end of a conversion result , and the default conditions of these bits are defined in table 15 . the status bits must be enabled in the register setting. when the overvoltage clamp flag is a 0 , it indicat es an overvoltage condition . the overvoltage clamp flag status bit updates on a per conversion basis. the sdo line goes to high - z after the sixth status bit is clocked out (except in daisy - chain mode). the user is not required to clock out all status bits to start the next conversion. the serial interface timing for cs m ode, 3 - w ire without busy indicator , including status bits , is shown in figure 49. table 15. sta tus b its ( d efault condition s ) bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 overvoltage ( ov ) clamp flag span compression high - z mode turbo mode reserved reserved sdo d17 d16 d15 d1 d0 sck 1 2 3 16 17 18 t sck t sck l t sckh t hsdo t dsdo cn v conversion acquisition t cyc acquisition sdi = 1 t cnvh t acq t en 23 24 t quiet2 status bits b[5:0] b1 t dis b0 22 t conv 14957-024 figure 49 . cs mode, 3 - wire without busy indicator serial interface timing diagram i ncluding status bits (sdi high)
data sheet ad4003 rev. 0 | page 25 of 33 cs mode, 3- wire turbo mode this mode is typically used when a single ad4003 is connected to an spi - compatible digital host. it provides additional time during the end of the adc conversion process to clock out the previous conversion result, providing a lower sck rat e. t he ad4003 can achieve a throughput rate of 2 msps only when turbo mode is enabled and using a minimum sck rate of 75 mhz . the timing diagram is shown in f igure 50. this mode replaces the 3 - wire with b usy indicator mode by programming the turbo mode bit , b it 1 (s ee table 14 ). when sdi is forced high, a rising edge on cnv initiates a conversion. the previous conversion data is available to read after the cnv rising edge. t he user must wait t quiet 1 time after cnv is brought high before bringing cnv low to clock out the previous conversion result. the user must also wait t quiet2 time after the last falling edge of sck to when cnv is brought high. when the conversion is complete, the ad4003 enters the acquisition phase and powers down. when cn v goes low, the msb is output to sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck e dges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster rea ding rate, provided it has an acceptable hold time. after the 18 th sc k falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. sdi = 1 t cyc cnv aquisition aquisition t acq t sck t sck l conversion sck d0 d1 d15 d16 d17 sdo t en t hsdo 1 2 3 16 17 18 t dsdo t dis t sckh t quiet1 quiet2 conv 14957-029 figure 50 . cs mode, 3 - wire turbo mode serial interface timing diagram (sdi high)
ad4003 data sheet rev. 0 | page 26 of 33 cs mode, 3-wire without busy indicator this mode is typically used when a single ad4003 is connected to an spi-compatible digital host. the connection diagram is shown in figure 51, and the corresponding timing diagram is shown in figure 52. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. after a conversion is initiated, it continues until completion irrespective of the state of cnv. this feature can be useful, for instance, to bring cnv low to select other spi devices, such as analog multiplexers; however, cnv must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad4003 enters the acquisition phase and powers down. when cnv goes low, the msb is output onto sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 18 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. there must not be any digital activity on sck during the conversion. ad4003 sdi sdo cnv sck convert data in clk digital host v io 14957-025 figure 51. cs mode, 3-wire without busy indicator connection diagram (sdi high) sdo d17 d16 d15 d1 d0 t dis sck 1 2 3 16 17 18 t sck t sckl t sckh t hsdo t dsdo cnv conversion a cquisition t cyc acquisition sdi = 1 t cnvh t acq t en t quiet2 t conv 14957-026 figure 52. cs mode, 3-wire without busy indicator serial interface timing diagram (sdi high)
data sheet ad4003 rev. 0 | page 27 of 33 cs mode, 3-wire with busy indicator this mode is typically used when a single ad4003 is connected to an spi-compatible digital host with an interrupt input ( irq ). the connection diagram is shown in figure 53, and the corresponding timing diagram is shown in figure 54. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. sdo is maintained in high impedance until the completion of the conversion irrespective of the state of cnv. prior to the minimum conversion time, cnv can select other spi devices, such as analog multiplexers; however, cnv must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull-up resistor on the sdo line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. the ad4003 then enters the acquisition phase and powers down. the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the optional 19 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. if multiple ad4003 devices are selected at the same time, the sdo output pin handles this contention without damage or induced latch-up. meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. there must not be any digital activity on the sck during the conversion. sdi sdo cnv sck convert data in clk digital host vio irq vio 47k ? ad4003 14957-027 figure 53. cs mode, 3-wire with busy indicator connection diagram (sdi high) sdo d17 d16 d1 d0 t dis sck 1 2 3 17 18 19 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq t quiet2 14957-028 figure 54. cs mode, 3-wire with busy indicator serial interface timing diagram (sdi high)
ad4003 data sheet rev. 0 | page 28 of 33 cs mode, 4- wire turbo mode this mode is typically used when a single ad4003 is connected to an spi - compatible digital host . it provides additional time during the end of the adc conversion process to clock out the previous conversion result , giving a lower sck rate. the ad4003 c an achieve a throughput rate of 2 msps on ly when turbo mode is enabled and using a minimum sck rate of 75 mhz . the timing diagram is shown in figure 55 . this mode replaces the 4 - wire with bu sy indicator mode by programming the turbo mode bi t , b it 1 (s ee table 14) . the previous conversion data is available to read after th e cnv rising edge. t he user must wait t quiet1 time after cnv is brought high before bringing sdi low to clock out the previous conv ersion result. the user must also wait t quiet2 time after the last falling edge of sck to when cnv is brought high. when the co nversion is complete, the ad4003 enters the acquisition phase and powers down. the adc result can be read by bringing its sdi input low, which consequently outputs the msb onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an ac ceptable hold time. after the 18 th sck falling edge or when sdi goes high ( whichever occurs first ) , sdo returns to high impedance. acquisition sdo sck acquisition sdi cnv t ssdicnv t hsdicnv t cyc t sck t sck l t en t hsdo 1 2 3 16 17 18 t dsdo t dis t sckh d17 d16 d15 d1 d0 t quiet1 t quiet2 t acq conversion t conv 14957-034 figure 55 . cs mode, 4 - wire turbo m ode timing diagram
data sheet ad4003 rev. 0 | page 29 of 33 cs mode, 4-wire without busy indicator this mode is typically used when multiple ad4003 devices are connected to an spi-compatible digital host. a connection diagram example using two ad4003 devices is shown in figure 56, and the corresponding timing is shown in figure 57. with sdi high, a rising edge on cnv initiates a conversion, selects cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback. if sdi and cnv are low, sdo is driven low. prior to the minimum conversion time, sdi can select other spi devices, such as analog multiplexers; however, sdi must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad4003 enters the acquisition phase and powers down. each adc result can be read by bringing its sdi input low, which consequently outputs the msb onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 18 th sck falling edge or when sdi goes high (whichever occurs first), sdo returns to high impedance and another ad4003 can be read. ad4003 sdi sdo cnv sck ad4003 sdi sdo cnv sck device b device a convert data in clk digital host cs1 cs2 14957-030 figure 56 . cs mode, 4-wire without busy indicator connection diagram sdo d17 d16 d15 d1 d0 t dis sck 12 3 34 35 36 t hsdo t dsdo t en conversion a cquisition t conv cyc t acq acquisition sdi(cs1) cnv t ssdicnv t hsdicnv d1 16 17 t sck t sckl t sckh d0 d17 d16 19 20 18 sdi(cs2) t quiet2 14957-031 figure 57 . cs mode, 4-wire without busy indicator serial interface timing diagram
ad4003 data sheet rev. 0 | page 30 of 33 cs mode, 4-wire with busy indicator this mode is typically used when a single ad4003 is connected to an spi-compatible digital host with an interrupt input, and when it is desired to keep cnv, which samples the analog input, independent of the signal used to select the data reading. this independence is particularly important in applications where low jitter on cnv is desired. the connection diagram is shown in figure 58, and the corresponding timing is shown in figure 59. with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback. if sdi and cnv are low, sdo is driven low. prior to the minimum conversion time, sdi can select other spi devices, such as analog multiplexers; however, sdi must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull-up resistor on the sdo line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. the ad4003 then enters the acquisition phase and powers down. the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the optional 19 th sck falling edge or when sdi goes high (whichever occurs first), sdo returns to high impedance. ad4003 sdi sdo cnv sck convert data in clk digital host irq vio 47k ? cs1 14957-032 figure 58 . cs mode, 4-wire with busy indicator connection diagram sdo d17 d16 d1 d0 t dis sck 123 171819 t sck t sckl t sckh t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi cnv t ssdicnv t hsdicnv t quiet2 14957-033 figure 59. cs mode, 4-wire with busy indicator serial interface timing diagram
data sheet ad4003 rev. 0 | page 31 of 33 daisy-chain mode use this mode to daisy-chain multiple ad4003 devices on a 3-wire or 4-wire serial interface. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using two ad4003 devices is shown in figure 60, and the corresponding timing is shown in figure 61. when sdi and cnv are low, sdo is driven low. with sck low, a rising edge on cnv initiates a conversion, selects daisy-chain mode, and disables the busy indicator. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when the conversion is complete, the msb is output onto sdo and the ad4003 enters the acquisition phase and powers down. the remaining data bits stored in the internal shift register are clocked out of sdo by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck rising edges. each adc in the daisy-chain outputs its data msb first, and 18 n clocks are required to read back the n adcs. the data is valid on both sck edges. the maximum conversion rate is reduced due to the total readback time. it is possible to write to each adc register in daisy-chain mode. the timing diagram is shown in figure 48. this mode requires 4-wire operation because data is clocked in on the sdi line with cnv held low. the same command byte and register data can be shifted through the entire chain to program all adcs in the chain with the same register contents, which requires 8 (n + 1) clocks for n adcs. it is possible to write different register contents to each adc in the chain by writing to the furthest adc in the chain, first using 8 (n + 1) clocks, and then the second furthest adc with 8 n clocks, and so forth until reaching the nearest adc in the chain, which requires 16 clocks for the command and register data. it is not possible to read register contents in daisy-chain mode; however the 6 status bits can be enabled if the user wants to know the adc configuration. note that enabling the status bits requires 6 extra clocks to clock out the adc result and the status bits per adc in the chain. turbo mode cannot be used in daisy-chain mode. convert data in clk digital host device b device a ad4003 sdi sdo cnv sck ad4003 sdi sdo cnv sck 14957-036 figure 60. daisy-chain mode connection diagram sdo a = sdi b d a 17 d b 17 d b 16 d b 15 d a 16 d a 15 d a 1d a 0 d a 1d a 0 d b 1d b 0 sck 1 2 3 343536 t ssdisck t hsdisck conversion acquisition t conv t cyc t acq acquisition cnv 16 17 t sck t sckl t sckh 19 20 18 sdi a = 0 sdo b d a 17 d a 16 t hsdo t dsdo t quiet2 t hsckcnv t dis t quiet2 t en 14957-037 figure 61. daisy-chain mode serial interface timing diagram
ad4003 data sheet rev. 0 | page 32 of 33 layout guidelines the pcb that houses the ad4003 must be designed so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the ad4003 , with its analog signals on the left side and its digital signals on the right side, eases this task. avoid running digital lines under the device because they couple noise onto the die, unless a ground plane under the ad4003 is used as a shield. fast switching signals, such as cnv or clocks, must not run near analog signal paths. avoid crossover of digital and analog signals. at least one ground plane must be used. it can be common or split between the digital and analog sections. in the latter case, join the planes underneath the ad4003 devices. the ad4003 voltage reference input (ref) has a dynamic input impedance. decouple the ref pin with minimal parasitic inductances by placing the reference decoupling ceramic capacitor close to (ideally right up against), the ref and gnd pins and connect them with wide, low impedance traces. finally, decouple the vdd and vio power supplies of the ad4003 with ceramic capacitors, typically 100 nf, placed close to the ad4003 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. an example of a layout following these rules is shown in figure 62 and figure 63. evaluating the ad4003 performance other recommended layouts for the ad4003 are outlined in the documentation of the evaluation board for the ad4003 ( eval-ad4003fmcz ). the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval-sdp-ch1z . 14957-038 figure 62 . example layout of the ad4003 (top layer) 14957-039 figure 63 . example layout of the ad4003 (bottom layer)
data sheet ad4003 rev. 0 | page 33 of 33 outline dimensions compliant to jedec standards mo-187-ba 091709 -a 6 0 0.70 0.55 0.40 5 1 0 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.0 0 2.90 copla narit y 0.10 0.23 0.13 3.1 0 3.00 2.90 5.15 4.9 0 4.65 pin 1 identifier 15 max 0.95 0.85 0.7 5 0.15 0.05 figure 64 . 10 - lead mini small outline package [msop] (rm - 10) dimensions shown in millimeters 2.48 2.38 2.23 0.50 0.40 0.30 10 1 6 5 0.30 0.25 0.20 pin 1 index are a se a ting plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pa d 3.10 3.00 sq 2.90 pin 1 indic a t or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 02-05-2013-c t o p view bottom view 0.20 min figure 65 . 10 - lead lead frame chip scale package [lfcsp] 3 mm 3 mm body and 0.75 mm package height (cp - 10 - 9) dimensions shown in millimeters ordering guide model 1 integral nonlinearity (inl) temperature range ordering quantity package description package option branding ad4003 brmz 1.0 lsb ?40c to +125c tube, 50 10- lead msop rm -10 c8c ad4003 brmz - rl7 1.0 lsb ?40c to +125c reel, 1000 10- lead msop rm -10 c8c ad4003bcpz - rl7 1.0 lsb ?40c to +125c reel, 1500 10- lead lfcsp cp -10-9 c8c eval - ad4003fmcz ad4003 evaluation board compatible with eval - sdp - ch1z 1 z = rohs compliant part. ? 2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d14957 - 0 - 10/16

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